4.5V - 5.5V ZiLOG IC Chip Z85C3008PEG For Electric Components

Electronic IC Chip ZiLOG Z85C3008PEG

Characteristic:

Z85C30: Optimized for non-multiplexed bus microprocessors
Z80C30: Optimized for Multiplexed Bus Microprocessors
Pin compatible with NMOS models
Two independent 0 to 4.1Mbps full-duplex channels, each with independent crystal oscillator, baud rate generator (BRG), and digital phase-locked loop (DPLL) for clock recovery
Multiprotocol operation under program control; programmable for NRZ, NRZI or FM data encoding
Asynchronous mode with 5 to 8 bits and 1, 1½ or 2 stop bits per character, programmable clock factor, interrupt detection and generation; parity, overrun and framing error detection
Sync mode, internal or external character synchronization on 1 or 2 sync characters, and CRC generation and checking via CRC-16 or CRC-CCITT preset to 1s or 0s
SDLC/HDLC mode with comprehensive frame-level control, automatic zero insertion and deletion, I-Field residual handling, abort generation and detection, CRC generation and checking, and SDLC looping
Software interrupt acknowledgement function (NMOS not available)
Local loopback and auto echo mode
Support T1 digital trunk76
Enhanced DMA support (NMOS not available), 10x19-bit status FIFO and 14-bit byte counter
speed:
Z85C3O: 8.5MHz, 10MHz and 16.384MHz
Z80C3O: 8MHz and 10MHz

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